In recent years, with the miniaturization of semiconductor devices, variations in the characteristics of devices have been increased, and therefore it is becoming difficult to secure a margin of operating frequency of and ensure power consumption of a digital circuit unit on a semiconductor integrated circuit. Moreover, also in terms of an analog circuit, since the power supply voltage has been decreased due to recent years' decrease in power consumption, it is becoming difficult to design a reference voltage generation circuit or reference current generation circuit for counteracting variations in the characteristics of devices and ensuring a fixed output.
It is known that a substrate voltage control technique is effective for securing a margin of operating frequency of and ensuring power consumption of a digital circuit. This is a technique that reduces variations in the characteristics of devices by changing the substrate voltages of chips whose operating frequency and power consumption deviate from the specifications, and aims to obtain characteristics close to the specifications. A variation reduction method for an analog circuit depends on the content of each circuit. As an example, in terms of a digital-to-analog converter, if a reference voltage generation circuit cannot reduce variations in the characteristics of PMOS transistors and NMOS transistors, the amplitude of an output depends on the characteristic variation and varies. In this case, a digital code inputted to the digital-to-analog converter is multiplied in advance by a correction parameter in accordance with the characteristic variations of PMOS and NMOS transistors; accordingly, the influence of the characteristic variations can be reduced. It is necessary to separately estimate the characteristic variations of PMOS and NMOS transistors for each chip in order to execute the correction process.